1. Field of the Invention
The present invention relates to a bidirectional input/output buffer, and more particularly, to a bidirectional input/output buffer for impedance matching, which allows data to be simultaneously sent and received over a single transmission line between two chips in a current-mode.
2. Description of the Related Art
As processes for fabricating integrated circuits improve, the performance of systems for achieving high speed operation may be significantly limited by the data transmission speed between chips. A bidirectional input/output buffer, a type of input/output buffer for data transmission, simultaneously sends and receives data over a single cable so that transmission performance of each single cable is doubled, and recovers only the received signals from the outside.
FIG. 1 is a schematic diagram showing the structure of a signal transmission system of a conventional bidirectional input/output buffer circuit. Bidirectional input/output buffers are respectively provided in chips 100A and 100B for transmission of data between the two chips 100A and 100B which are coupled to a transmission line having an impedance Z.sub.0 in FIG. 1. The bidirectional input/output buffers include; transmitting terminals to which transmission signals IN1 and IN2, to be sent to other chips, are applied; input/output nodes OUT1 and OUT2 through which signal voltages are sent to other chips and signal voltages from the other chips are received; recovering terminals RET1 arid RET2 at which the received signals from other chips have recovered original values; reference voltage generators 103a and 103b for respectively generating reference voltages Vref1 and Vref2 which are selected according to voltages of the transmission signals IN1 and IN2 and which are respectively compared with voltage values of the input/output nodes OUT1 and OUT2 each having a voltage value in which the signal to be transmitted outwardly and the signal received from the outside are mixed, to recover the signals received from the outside in the two chips 100A and 100B; output buffers 101a and 101b for respectively buffering the transmission signals IN1 and IN2; and voltage comparators 102a and 102b for comparing the reference voltages from the reference voltage generators 103a and 103b with the voltages of the input/output nodes OUT1 and OUT2 respectively.
In the operation of the signal transmission system of FIG. 1, voltages applied to the input/output nodes OUT1 and OUT2 according to the transmission signal IN1 to be outwardly transmitted and the signal IN2 received from the outside in one chip 100A, appear to be the average value of signal voltages transmitted by the two chips 100A and 100B. At this time, assuming that the voltage values transmitted between the two chips 100A and 100B are classified into only two levels, 0 volts and a high level voltage having a predetermined value, the input/output node OUT1 has a high level voltage, a 1/2 high level voltage or 0. The voltages of the input/output nodes OUT1 and OUT2 are respectively compared with the reference values Vref 1 and Vref 2 which are generated by the reference voltage generators 103a and 103b according to the transmission signals IN1 and IN2, to provide original signal levels. Table 1 shows the reference voltages Vref1 and Vref2, which depend on the voltage values of the transmission signals IN1 and IN2, and signal values recovered from the level values of the input/output nodes OUT1 and OUT2 at the recovering terminals RET1 and RET2 in the conventional, bidirectional input/output buffers.
TABLE 1 IN1 High High Low Low IN2 High Low High Low OUT1, OUT2 VDD 0.5 VDD 0.5 VDD 0 Vref1 0.75 VDD 0.75 VDD 0.25 VDD 0.25 VDD Vref2 0.75 VDD 0.25 VDD 0.75 VDD 0.25 VDD RET1 High Low High Low RET2 High High Low Low
It can be known from Table 1 that the transmission signals IN1 and IN2 are respectively transmitted to the corresponding recovering terminals RET2 and RET1 of the other chips at the same level value. However, since conventional bidirectional input/output buffers operate in a voltage-mode, full voltage swing appears at nodes which have capacitor components in the circuits of the bidirectional input/output buffers. In this situation, switching speed is slowed down, which causes the transmission speed of the bidirectional buffer to be limited.